High-density non-volatile memory arrays can be used to store digital data for computing systems, such as computers, mobile telephones, personal digital assistants, music players, other electronic devices, or any combination thereof. In an example, the memory arrays may include multiple transistor cells, where each transistor cell can include a floating gate adapted to retain an electrical charge representative of a data value when power is removed from the transistor cell. Bit-lines, word lines, and reference lines (i.e., wire traces, active/diffusion reference lines, other electrical interconnections, or any combination thereof, hereinafter generally referred to as “lines”) may be used in various combinations to store data to and retrieve data from the transistor cells.
Unfortunately, as the size of the memory arrays has decreased and the transistor cell density has increased, routing of such lines has become increasingly complex. Further, such lines can contribute to undesired power consumption within a particular array and may adversely impact read margins. In particular, the wire traces may introduce undesired impedances, which can reduce sensed-voltage-level read margins, for example.
Additionally, the transistors within the array may contribute to overall power consumption. For example, charging and discharging of gate and interconnect capacitances can dissipate a significant amount of power. Further, parasitic leakage through the reverse bias P/N junctions and/or through sub-threshold source-to-drain currents of metal-oxide semiconductor (MOS) transistors in an “off” state can also dissipate power.